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What we do, in detail

FPGA & ASIC digital design

Digital controller design for image sensors and ROICs

On-chip digital for global- and rolling-shutter CMOS sensors and infrared ROICs: timing generation, readout sequencing, exposure and mode control, register interfaces.

  • Global and rolling shutter timing, row and column sequencing, multi-mode operation
  • Exposure, gain and windowing control; test patterns; SPI or I²C register access with SystemRDL maps
  • Cycle-exact timing definitions the analog and layout teams can review, kept as the single source for RTL and documentation

Video bridging

Format conversion and aggregation between video interfaces: MIPI CSI-2 and DSI, SDI, parallel, USB, LVDS and SLVS-EC, HDMI.

  • Sensor-to-processor and camera-to-display bridges, usually on small FPGAs
  • Multi-sensor aggregation, virtual channels, pixel-format and bit-depth conversion, frame-rate adaptation
  • Physical-layer timing, constraints and bring-up on the target link

FPGA design, verification and bring-up

RTL design, self-checking testbenches with reference models, timing closure, and support on the bench until the board works.

  • SystemVerilog and Verilog RTL for AMD, Intel and Lattice devices
  • Reference models and bit-exact regressions under Verilator or commercial simulators
  • Debug, timing closure and bring-up on the target hardware; reviews of existing designs

Real-time image processing

Fixed-latency processing on FPGA and ASIC: scaling, non-uniformity and defect correction, statistics, overlays and on-screen display.

  • Streaming architectures with a stated latency and no more buffering than the function needs
  • Correction and calibration pipelines for infrared and CMOS imagers
  • On-screen display and menu overlays generated as verified RTL with OSD Design Studio

Low-power, low-noise analog PCB design

Sensor front-end and mixed-signal boards: power trees, references, biasing and clocking, with the layout discipline that keeps noise out of the image.

  • Power sequencing and low-noise regulation for sensors and ROICs
  • ADC and clock distribution, grounding and stack-up for imaging boards
  • Bring-up with measurements that tie back to the sensor specification

Camera hardware design

From sensor board to interface board: architecture, schematics, layout supervision, and design packages a partner or manufacturer can build from.

  • Sensor, processing and interface boards; flex, connector and mechanical interface planning
  • Power and thermal budgets, interface control documents between sensor, FPGA, processor and display
  • Design packages with requirements, pinouts, sequencing and test plans

Engagements

Fixed-scope block or board

One controller, bridge, pipeline stage or board: specified, designed, verified, handed over.

Verification of existing RTL

A model and testbench for a design you already have, with a report.

Specification phase

The document set that lets your team or a partner build the rest.

Retained days

An engineer on call, a fixed number of days per month.

Consultancy and design services

From a design review or a few days of expert advice to a complete block, board or verification package delivered and handed over. The usual first step is a one-hour call about the problem, followed by a short written proposal with scope, deliverables and a schedule.