linebuffer

OSD Design Studio

v1.0.0free in the browser

An on-screen display (OSD) design tool for FPGA and ASIC video pipelines: draw the overlay, try the menu live, and export it as verified Verilog.

Design the overlay on a canvas the size of your video’s active area, with text, readouts, markers, bars, icons and a menu, and run the menu with on-screen buttons on the same state machine the RTL is generated from.

Export a synthesizable Verilog or SystemVerilog overlay: video in, the same stream out with the OSD on it, fixed latency, no frame or line buffer. A self-checking testbench, with golden frames from the same renderer, comes with it.

OSD Design Studio: the designer with the menu open

Editions

Browser

Free. Design the overlay, run the menu and check the design rules, nothing to install. Projects stay in browser storage until you save them as a file. Export is reserved for the licensed versions.

Open in the browser

Desktop

Licensed. A native window with real file dialogs for Linux and Windows, full RTL and testbench export, works offline.

Ask for a licence

Command line

Licensed. Headless export, render, verify, info and validate; runs the generated testbench under Verilator, so it fits a regression flow.

Ask for a licence

What the generated module connects to

clk Video stream in parallel video or AXI4-Stream Bindings plain ports AXI4-Lite registers readout values, enum states, visibility flags, menu buttons OSD overlay generated RTL fixed clock latency no frame buffer Video stream out same format and timing, OSD drawn on it

Video stream in

Parallel video or AXI4-Stream, grayscale or RGB, at the resolution set in the project.

Bindings

The live values the OSD shows: readouts, enumerated states, visibility flags and the menu buttons. Delivered as plain top-level ports, or written through an AXI4-Lite register map that the export generates and documents.

Video stream out

The same stream, same format and timing, a fixed number of clock cycles later, with the OSD drawn on it. No frame or line buffer, so latency is constant and memory is not needed.

Screens

OSD Design Studio: Designer: canvas over a sample frame, element list, inspector
Designer: canvas over a sample frame, element list, inspector
OSD Design Studio: Designer with the menu open and the run-time state panel
Designer with the menu open and the run-time state panel
OSD Design Studio: Menu: pages, items and the navigation state machine
Menu: pages, items and the navigation state machine
OSD Design Studio: Assets: fonts, icons and sample frames
Assets: fonts, icons and sample frames
OSD Design Studio: Project: video format, colour, interfaces
Project: video format, colour, interfaces
OSD Design Studio: Export: RTL, package, ROM images, testbench and register map
Export: RTL, package, ROM images, testbench and register map

What it does

Designer
Canvas over a sample frame (PNG, PGM, PPM or a test pattern), element list with z-order, inspector, direct manipulation, screens, pixel grid and zoom.
Elements
Static text, numeric readout, enumerated text, rectangle, line, crosshair, bitmap and icon, bar, and the menu list; blend modes opaque, keyed, invert and half; visibility conditions with blink; grayscale or RGB.
Menu
Pages and items (sub-page, back, action, confirm, toggle, enum, number, value, separator, exit), a fixed navigation state machine with debounce, long-press repeat and acceleration, timeouts and shortcuts.
Run-time state
Set every binding, press the buttons, and watch the same state machine the RTL is generated from.
Export
SystemVerilog or Verilog RTL for parallel video or AXI4-Stream, optional simple or AXI4-Lite register interface, package or header, ROM images, testbench with golden frames, summary and register map.
Verification
The generated testbench compares every output frame with the renderer’s golden image; the command-line version runs it under Verilator.

Availability

The browser version is free for designing and simulating. Export, the desktop application and the command line are licensed; write for pricing and a trial.

Questions

What is OSD Design Studio?

A design tool for on-screen displays (OSD) in FPGA and ASIC video pipelines. You lay out text, readouts, markers, bars, icons and a menu over a sample frame, run the menu with on-screen buttons, and export a synthesizable Verilog or SystemVerilog overlay module together with a self-checking testbench.

Does the generated OSD overlay need a frame buffer?

No. The overlay is a streaming module: video in, the same video out with the OSD drawn on it, after a fixed clock latency. It needs no frame buffer and no external memory, which keeps latency constant and resource use small.

Which video interfaces does the OSD module support?

Parallel video and AXI4-Stream, in grayscale or RGB, at the resolution you set in the project. Bindings, the live values the OSD shows, arrive either as plain top-level ports or through an AXI4-Lite register map that the export generates and documents.

How is the exported RTL verified?

The export includes a self-checking SystemVerilog testbench whose golden frames come from the same renderer you designed with, so the hardware is compared against the picture you saw, bit for bit. The command-line edition runs it under Verilator.

Is OSD Design Studio free?

The browser edition is free for designing and simulating. Export, the desktop application and the command-line edition are licensed. Write to hello@linebuffer.com for pricing and a trial.

Can I use it for an OSD menu with buttons?

Yes. Menus have pages and items (sub-page, back, action, confirm, toggle, enum, number, value, separator, exit) driven by a navigation state machine with debounce, long-press repeat and timeouts, and the same state machine is generated into the RTL.

Questions about OSD Design Studio?

Write with what you are trying to build; a short answer usually comes back the same day.